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512kx36 & 1mx18 pipelined n t ram tm - 1 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary document title 512kx36 & 1mx18-bit pipelined n t ram tm the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 0.0 0.1 0.2 0.3 0.4 remark advance preliminary preliminary preliminary preliminary history 1. initial document. 1. update the current spec(icc, i sb ) 1. change the isb,isb1,isb2 - isb ; from 120ma to 170ma - isb1 ; from 80ma to 150ma - isb2 ; from 80ma to 130ma 1. remove the 1.8v vdd voltage level 1. remove the -20 and -13 speed bin draft date mar. 23, 2004 may. 13, 2004 sep. 21. 2004 oct. 18, 2004 jan. 04, 2005
512kx36 & 1mx18 pipelined n t ram tm - 2 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary 16mb ntram(flow through / pipelined) ordering informa tion org. part number mode vdd speed ft ; access time(ns) pipelined ; cycle time(mhz) pkg temp 1mx18 k7m161835b-qc(i)65 flowthrough 3.3/2.5 6.5ns q : 100tqfp f : 165fbga c ; commercial temp.range i ; industrial temp.range k7n161831b-q(f)c(i)25/16 pipelined 3.3/2.5 250/167mhz 512kx36 k7m163635b-qc(i)65 flowthrough 3.3/2.5 6.5ns k7n163631b-q(f)c(i)25/16 pipelined 3.3/2.5 250/167mhz
512kx36 & 1mx18 pipelined n t ram tm - 3 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary 512kx36 & 1mx18-bit pipelined n t ram tm the k7n163631b and k7n161831b are 18,874,368-bits syn- chronous static srams. the n t ram tm , or no turnaround random access memory uti- lizes all the bandwidth in any combination of operating cycles. address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. burst order control must be tied "high or low". asynchronous inputs include the sleep mode enable(zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. for read cycles, pipelined sram output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. the k7n163631b and k7n161803b are implemented with samsung s high performance cmos technology and is avail- able in 100pin tqfp and 165fbga packages. multiple power and ground pins minimize ground bounce. general description features logic block diagram v dd = 2.5 or 3.3v +/- 5% power supply. byte writable function. enable clock and suspend operation. single read/write control pin. self-timed write cycle. three chip enable for simple depth expansion with no data- contention . a interleaved burst or a linear burst mode. asynchronous output enable control. power down mode. 100-tqfp-1420a 165fbga(11x15 ball aray) with body size of 13mmx15mm. operating in commeical and industrial temperature range. fast access times parameter symbol -25 -16 unit cycle time tcyc 4.0 6.0 ns clock access time tcd 2.6 3.5 ns output enable access time toe 2.6 3.5 ns we bw x clk cke cs 1 cs 2 cs 2 adv oe zz dqa 0 ~ dqd 7 or dqa 0 ~ dqb 8 address address register control logic a 0 ~a 1 36 or 18 dqpa ~ dqpd output buffer register data-in register data-in register k k k register burst address counter write address register write control logic control register k a [0:18]or a [0:19] lbo a 2 ~a 18 or a 2 ~a 19 a 0 ~a 1 (x=a,b,c,d or a,b) 512kx36, 1mx18 memory array n t ram tm and no turnaround random access memory are trademarks of samsung.
512kx36 & 1mx18 pipelined n t ram tm - 4 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) nc/dqpc dqc 0 dqc 1 v ddq v ssq dqc 2 dqc 3 dqc 4 dqc 5 v ssq v ddq dqc 6 dqc 7 v dd v dd v dd v ss dqd 0 dqd 1 v ddq v ssq dqd 2 dqd 3 dqd 4 dqd 5 v ssq v ddq dqd 6 dqd 7 nc/dqpd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb/nc dqb 7 dqb 6 v ddq v ssq dqb 5 dqb 4 dqb 3 dqb 2 v ssq v ddq dqb 1 dqb 0 v ss v dd v dd zz dqa 7 dqa 6 v ddq v ssq dqa 5 dqa 4 dqa 3 dqa 2 v ssq v ddq dqa 1 dqa 0 dqpa/nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 a 6 a 7 cs 1 cs 2 bw d bw c bw b bw a cs 2 v dd v ss clk we cke oe adv a 18 a 17 a 8 81 a 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 a 16 a 15 a 14 a 13 a 12 a 11 a 10 n.c. n.c. v dd v ss n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 31 lbo pin name note : 1. a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 18 adv we clk cke cs 1 cs 2 cs 2 bw x(x=a,b,c,d) oe zz lbo address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control 32,33,34,35,36,37,44 45,46,47,48,49,50,81 82,83,84,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 v dd v ss n.c. dqa 0 ~a 7 dqb 0 ~b 7 dqc 0 ~c 7 dqd 0 ~d 7 dqpa~p d or nc v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs output power supply (3.3v or 2.5v) output ground 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 k7n163631b(512kx36)
512kx36 & 1mx18 pipelined n t ram tm - 5 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) n.c. n.c. n.c. v ddq v ssq n.c. n.c. dqb 8 dqb 7 v ssq v ddq dqb 6 dqb 5 v dd v dd v dd v ss dqb 4 dqb 3 v ddq v ssq dqb 2 dqb 1 dqb 0 n.c. v ssq v ddq n.c. n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a 10 n.c. n.c. v ddq v ssq n.c. dqa 0 dqa 1 dqa 2 v ssq v ddq dqa 3 dqa 4 v ss v dd v dd zz dqa 5 dqa 6 v ddq v ssq dqa 7 dqa 8 n.c. n.c. v ssq v ddq n.c. n.c. n.c. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 a 6 a 7 cs 1 cs 2 bw b bw a cs 2 v dd v ss clk we cke oe adv a 19 a 18 a 8 81 a 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 a 17 a 16 a 15 a 14 a 13 a 12 a 11 n.c. n.c. v dd v ss n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 31 lbo k7n161831b(1mx18) n.c. n.c. pin name n ote : a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 19 adv we clk cke cs 1 cs 2 cs 2 bw x(x=a,b) oe zz lbo address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control 32,33,34,35,36,37,44 45,46,47,48,49,50,80 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 v dd v ss n.c. dqa 0 ~a 8 dqb 0 ~b 8 v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs data inputs/outputs output power supply (3.3v or 2.5v) output ground 14,15,16,41,65,66,91 17,40,67,90 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,95,96 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
512kx36 & 1mx18 pipelined n t ram tm - 6 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary 165-pin fbga package configurations (top view) pin name symbol pin name symbol pin name a a 0 ,a 1 adv we clk cke cs 1 cs 2 cs 2 bw x (x=a,b,c,d) oe zz lbo tck tms tdi tdo address inputs burst address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqc dqd dqpa~pd v ddq power supply ground no connect data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs output power supply k7n163631b(512kx36) note : * a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. 1234 567891011 a nc a cs 1bw cbw b cs 2 cke adv a a nc b nc a cs2 bw dbw aclk we oe aanc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc v dd nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa p nc nc a a tdi a 1 *tdoaaanc r lbo nc a a tms a 0 *tckaaaa
512kx36 & 1mx18 pipelined n t ram tm - 7 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary pin name symbol pin name symbol pin name a a 0 ,a 1 adv we clk cke cs 1 cs 2 cs 2 bw x (x=a,b) oe zz lbo tck tms tdi tdo address inputs burst address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqpa, pb v ddq power supply ground no connect data inputs/outputs data inputs/outputs data inputs/outputs output power supply 165-pin fbga package configurations (top view) k7n161831b(1mx18) note : * a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired. 1234 567891011 a nc a cs 1bw bnc cs 2 cke advaaa b nc a cs2 nc bw aclk we oe aanc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpa d nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa e nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa f nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa g nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa h nc v dd nc v dd v ss v ss v ss v dd nc nc zz j dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc n dqpb nc v ddq v ss nc nc nc v ss v ddq nc nc p nc nc a a tdi a 1 *tdoaaanc r lbo nc a a tms a 0 *tckaaaa
512kx36 & 1mx18 pipelined n t ram tm - 8 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary function description the k7n163631b and k7n161831b are n t ram tm designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe , lbo and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be internally generated by t he burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for nex t operation. clock enable(cke ) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. n t ram tm latches external address and initiates a cycle, when cke , adv are driven to low and all three chip enables(cs 1 , cs 2 , cs 2 ) are active . output enable(oe ) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in th e address register, cke is driven low, all three chip enables(cs 1 , cs 2 , cs 2 ) are active, the write enable input signals we are driven high, and adv driven low.the internal array is read between the first rising edge and the second rising edge of the clock and t he data is latched in the output register. at the second clock edge the data is driven out of the sram. also during read operation oe must be driven low for the device to drive out the requested data. write operation occurs when we is driven low at the rising edge of the clock. bw [d:a] can be used for byte write operation. the pipe- lined n t ram tm uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associated with that address is required two cycle later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram normally operates after 2 cycles of wake u p time. burst sequence table (interleaved burst, lbo =high) lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 bq table (linear burst, lbo =low) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
512kx36 & 1mx18 pipelined n t ram tm - 9 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary state diagram for n t ram tm begin write burst write begin read write d s r e a d burst read d s w r i t e d s read d s re a d ds write burst deselect b u r s t r e a d b u r s t w r i t e read write burst burst notes : 1. an ignore clock edge cycle is not shown is the above diagram. this is because cke high only blocks the clock(clk) input and does not change the state of the device. 2. states change on the rising edge of the clock(clk) command action ds deselect read begin read write begin write burst begin read begin write continue deselect
512kx36 & 1mx18 pipelined n t ram tm - 10 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary synchronous truth table notes : 1. x means "don t care". 2. the rising edge of clock is symbolized by ( ). 3. a continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adv we bw x oe cke clk address accessed operation hxxlxxx l n/a not selected xlxlxxx l n/a not selected xxhlxxx l n/a not selected xxxhxxx l n/a not selected continue lhllhxl l external address begin burst read cycle xxxhxxl l next address continue burst read cycle lhllhxh l external address nop/dummy read xxxhxxh l next address dummy read lhllllx l external address begin burst write cycle xxxhxlx l next address continue burst write cycle lhlllhx l n/a nop/write abort xxxhxhx l next address write abort xxxxxxx h current address ignore clock write truth table (x36) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( ). we bw a bw b bw c bw d operation hxxxx read llhhh write byte a lhlhh write byte b lhhlh write byte c lhhhl write byte d lllll write all bytes l h h h h write abort/nop truth tables write truth table (x18) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( ). we bw a bw b operation hxx read l l h write byte a l h l write byte b l l l write all bytes l h h write abort/nop
512kx36 & 1mx18 pipelined n t ram tm - 11 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary asynchronous truth table operation zz oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes 1. x means "don t care". 2. sleep mode means power sleep mode of which stand-by current does not depend on cycle time. 3. deselected means power sleep mode of which stand-by current depends on cycle time. absolute maximum ratings* *notes : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.3 to 4.6 v voltage on any other pin relative to v ss v in -0.3 to v dd +0.3 v power dissipation p d 1.6 w storage temperature t stg -65 to 150 c operating temperature commercial t opr 0 to 70 c industrial t opr -40 to 85 c storage temperature range under bias t bias -10 to 85 c capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - tbd pf output capacitance c out v out =0v - tbd pf operating conditions (0 c t a 70 c) notes: 1. the above parameters are also guaranteed at industrial temperature range. 2. it should be v ddq v dd parameter symbol min typ. max unit supply voltage v dd1 2.375 2.5 2.625 v v ddq1 2.375 2.5 2.625 v v dd2 3.135 3.3 3.465 v v ddq2 3.135 3.3 3.465 v ground v ss 000v v ss v ih v ss- 1.0v 20% t cyc (min)
512kx36 & 1mx18 pipelined n t ram tm - 12 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary dc electrical characteristics notes : 1. the above parameters are also guaranteed at industrial temperature range. 2. reference ac operating conditions and characteristics for input and timing. 3. data states are all zero. 4. in case of i/o pins, the max. v ih =v ddq +0.3v parameter symbol test conditions min max unit notes input leakage current(except zz) i il v dd =max ; v in =v ss to v dd -2 +2 a output leakage current i ol output disabled, v out =v ss to v ddq -2 +2 a operating current i cc device selected, i out =0ma, zz v il , cycle time t cyc min -25 - 360 ma 1,2 -16 - 300 standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or v dd -0.2v -170ma i sb1 device deselected, i out =0ma, zz 0.2v, f=0, all inputs=fixed (v dd -0.2v or 0.2v) -150ma i sb2 device deselected, i out =0ma, zz v dd -0.2v, f=max, all inputs v il or v ih -130ma output low voltage(3.3v i/o) v ol i ol =8.0ma - 0.4 v output high voltage(3.3v i/o) v oh i oh =-4.0ma 2.4 - v output low voltage(2.5v i/o) v ol i ol =1.0ma - 0.4 v output high voltage(2.5v i/o) v oh i oh =-1.0ma 2.0 - v input low voltage(3.3v i/o) v il -0.3* 0.8 v input high voltage(3.3v i/o) v ih 2.0 v dd +0.3** v 3 input low voltage(2.5v i/o) v il -0.3* 0.7 v input high voltage(2.5v i/o) v ih 1.7 v dd +0.3** v 3 test conditions * the above parameters are also guaranteed at industrial temperature range. parameter value input pulse level(for 3.3v i/o) 0 to 3.0v input pulse level(for 2.5v i/o) 0 to 2.5v input rise and fall time(measured at 20% to 80% for 3.3/2.5v i/o) 1.0v/ns input and output timing reference levels for 3.3v i/o 1.5v input and output timing reference levels for 2.5v i/o v ddq /2 output load see fig. 1
512kx36 & 1mx18 pipelined n t ram tm - 13 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary ac timing characteristics notes : 1. the above parameters are also guaranteed at industrial temperature range. 2. all address inputs must meet the specified setup and hold times for all rising clock(clk) edges when adv is samp led low and cs is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. chip selects must be valid at each rising edge of clk(when adv is low) to remain enabled. 4. a write cycle is defined by we low having been registered into the device at adv low, a read cycle is defined by we high with adv low, both cases must meet setup and hold times. 5. to avoid bus contention, at a given voltage and temperature t lzc is more than t hzc. the specs as shown do not imply bus contention because t lzc is a min. parameter that is worst case at totally different test conditions (0 c,3.465v) than t hzc , which is a max. parameter(worst case at 70 c,3.135v) it is not possible for two srams on the same board to be at such different voltage and temperature. parameter symbol -25 -16 unit min max min max cycle time t cyc 4.0 - 6.0 - ns clock access time t cd - 2.6 - 3.5 ns output enable to data valid t oe - 2.6 - 3.5 ns clock high to output low-z t lzc 1.5 - 1.5 - ns output hold from clock high t oh 1.5 - 1.5 - ns output enable low to output low-z t lzoe 0-0-ns output enable high to output high-z t hzoe - 2.6 - 3.0 ns clock high to output high-z t hzc - 2.6 - 3.0 ns clock high pulse width t ch 1.7 - 2.2 - ns clock low pulse width t cl 1.7 - 2.2 - ns address setup to clock high t as 1.2 - 1.5 -ns cke setup to clock high t ces 1.2 - 1.5 -ns data setup to clock high t ds 1.2 - 1.5 -ns write setup to clock high (we , bw x )t ws 1.2 - 1.5 -ns address advance setup to clock high t advs 1.2 - 1.5 -ns chip select setup to clock high t css 1.2 - 1.5 - ns address hold from clock high t ah 0.3 - 0.5 - ns cke hold from clock high t ceh 0.3 - 0.5 - ns data hold from clock high t dh 0.3 - 0.5 - ns write hold from clock high (we , bw x )t wh 0.3 - 0.5 - ns address advance hold from clock high t advh 0.3 - 0.5 - ns chip select hold from clock high t csh 0.3 - 0.5 - ns zz high to power down t pds 2 - 2 - cycle zz low to power up t pus 2 - 2 - cycle output load(b), (for t lzc , t lzoe , t hzoe & t hzc ) dout 353 ? / 1538 ? 5pf* +3.3v for 3.3v i/o 319 ? / 1667 ? fig. 1 * including scope and jig capacitance output load(a) dout zo=50 ? rl=50 ? vl=1.5v for 3.3v i/o v ddq /2 for 2.5v i/o /+2.5v for 2.5v i/o
512kx36 & 1mx18 pipelined n t ram tm - 14 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary sleep mode sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb2 . the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. any operation pending when entering sleep mode is not guaranteed to successful complete. therefore, sleep mode (read or write) must not be initiated until valid pend- ing operations are completed. similarly, when exiting sleep mode during t pus , only a deselect or read cycle should be given while the sram is transitioning out of sleep mode. sleep mode electrical characteristics description conditions symbol min max units current during sleep mode zz v ih i sb2 tbd ma zz active to input ignored t pds 2 cycle zz inactive to input sampled t pus 2 cycle zz active to sleep current t zzi 2 cycle zz inactive to exit sleep current t rzzi 0 k t pds zz setup cycle t rzzi zz isupply all inputs (except zz) outputs (q) t zzi t pus zz recovery cycle deselect or read only high-z don t care i sb2 sleep mode waveform normal operation cycle deselect or read only
512kx36 & 1mx18 pipelined n t ram tm - 15 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg - ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up , therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap control ler without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may als o be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo tdi tms tck test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 bypass bypass register 4 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 bypass bypass register 4 1 1 1 bypass bypass register 4
512kx36 & 1mx18 pipelined n t ram tm - 16 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 512kx36 0000 00111 00100 xxxxxx 00001001110 1 1mx18 0000 01000 00011 xxxxxx 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bits 32 bits 75 bits 1mx18 3 bits 1 bits 32 bits 75 bits 165fbga boundary scan exit order(x36) 11rlbo clk 6b 39 2 6n nc nc 11b 40 311pnc nc 1a 41 48pa cs 26a 42 58ra bw a5b 43 69ra bw b5a 44 79pa bw c4a 45 8 10p a bw d4b 46 9 10r a cs2 3b 47 10 11r a cs 13a 48 11 11h zz a2a49 12 11n dqa a2b50 13 11m dqa nc 1b 51 14 11l dqa dqc 1c 52 15 11k dqa dqc 1d 53 16 11j dqa dqc 1e 54 17 10m dqa dqc 1f 55 18 10l dqa dqc 1g 56 19 10k dqa dqc 2d 57 20 10j dqa dqc 2e 58 21 11g dqb dqc 2f 59 22 11f dqb dqc 2g 60 23 11e dqb dqd 1j 61 24 11d dqb dqd 1k 62 25 10g dqb dqd 1l 63 26 10f dqb dqd 1m 64 27 10e dqb dqd 2j 65 28 10d dqb dqd 2k 66 29 11c dqb dqd 2l 67 30 11a nc dqd 2m 68 31 10a a dqd 1n 69 32 10b a a3p70 33 9a a a3r71 34 9b a a4r72 35 8a adv a4p73 36 8b oe a1 6p 74 37 7a cke a0 6r 75 38 7b we 165fbga boundary scan exit order(x18 ) 11rlbo clk 6b 39 2 6n nc nc 11b 40 311pnc nc 1a 41 48pa cs 26a 42 58ra bw a5b 43 69ra nc 5a 44 79pa bw b4a 45 810pa nc 4b 46 9 10r a cs2 3b 47 10 11r a cs 13a 48 11 11h zz a2a49 12 11n nc a2b50 13 11m nc nc 1b 51 14 11l nc nc 1c 52 15 11k nc nc 1d 53 16 11j nc nc 1e 54 17 10m dqa nc 1f 55 18 10l dqa nc 1g 56 19 10k dqa dqb 2d 57 20 10j dqa dqb 2e 58 21 11g dqa dqb 2f 59 22 11f dqa dqb 2g 60 23 11e dqa dqb 1j 61 24 11d dqa dqb 1k 62 25 11c dqa dqb 1l 63 26 10f nc dqb 1m 64 27 10e nc dqb 1n 65 28 10d nc nc 2k 66 29 10g nc nc 2l 67 30 11a a nc 2m 68 31 10a a nc 2j 69 32 10b a a3p70 33 9a a a3r71 34 9b a a4r72 35 8a adv a4p73 36 8b oe a1 6p 74 37 7a cke a0 6r 75 38 7b we note, nc ; don t care
512kx36 & 1mx18 pipelined n t ram tm - 17 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary jtag dc operating conditions note : the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 3.135/2.375 3.3/2.5 3.465/2.625 v input high level v ih 2.0/1.7 - v dd +0.3 v input low level v il -0.3 - 0.8/0.7 v output high voltage v oh 2.4/2.0 - - v output low voltage v ol - - 0.4/0.4 v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions parameter symbol min unit note input high/low level v ih /v il 3.0/0 , 2.5/0 v input rise/fall time tr/tf 1.0/1.0 , 1.0/1.0 ns input and output timing reference level v ddq /2 v tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
512kx36 & 1mx18 pipelined n t ram tm - 18 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary clock cke address write cs adv oe data out timing waveform of read cycle notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t ch t cl t ces t ceh t as t ah a1 a2 a3 t ws t wh t css t csh t oe t hzoe t lzoe t cd t oh t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc t advs t advh
512kx36 & 1mx18 pipelined n t ram tm - 19 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary timing waveform of wrte cycle clock address write cs adv data in t ch t cl a2 a3 d2-1 d1-1 d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 oe data out t ds t dh don t care undefined t cyc cke a1 d3-4 t ces t ceh notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l q0-4 t hzoe q0-3
512kx36 & 1mx18 pipelined n t ram tm - 20 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary timing waveform of single read/write clock address write cs adv oe data in t ch t cl t ds t dh data out a2 a4 a5 d2 t oe t lzoe q1 don t care undefined t cyc cke t ces t ceh a1 a3 a7 a6 q3 q4 q7 q6 d5 notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l a9 a8
512kx36 & 1mx18 pipelined n t ram tm - 21 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary timing waveform of cke operation clock address write cs adv oe data in t ch t cl data out a1 a2 a3 a4 a5 t ces t ceh don t care undefined t cyc cke t ds t dh d2 q4 q1 notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t cd t lzc t hzc q3 a6
512kx36 & 1mx18 pipelined n t ram tm - 22 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary timing waveform of cs operation clock address write cs adv oe data in t ch t cl data out a1 a2 a3 a4 a5 don t care undefined t cyc cke d5 q4 t ces t ceh q1 q2 t oe t lzoe d3 t cd t lzc notes : write = l means we = l, and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l, and cs 2 = l t hzc t dh t ds
512kx36 & 1mx18 pipelined n t ram tm - 23 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary package dimensions 0.10 max 0~8 22.00 0.30 20.00 0.20 16.00 0.30 14.00 0.20 1.40 0.10 1.60 max 0.05 min (0.58) 0.50 0.10 #1 (0.83) 0.50 0.10 100-tqfp-1420a 0.65 0.30 0.10 0.10 max + 0.10 - 0.05 0.127 units ; millimeters/inches
512kx36 & 1mx18 pipelined n t ram tm - 24 - rev 0.4 jan. 2005 k7n161831b k7n163631b preliminary 165 fbga package dimensions c side view 13mm x 15mm body, 1.0mm bump pitch, 11x15 ball array f a ? h g b bottom view top view a b d e e symbol value units note symbol value units note a 15 0.1 mm e 1.0 mm b 13 0.1 mm f 14.0 mm c 1.3 0.1 mm g 10.0 mm d 0.35 0.05 mm h 0.5 0.05 mm

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